ΠΠΎ ΡΡΠ»ΠΎΠ²ΠΈΡ Π·Π°Π΄Π°Π½ΠΈΡ Π½Π΅ΠΎΠ±Ρ
ΠΎΠ΄ΠΈΠΌΠΎ ΡΠ΅Π°Π»ΠΈΠ·ΠΎΠ²Π°ΡΡ ΠΎΠΏΠ΅ΡΠ°ΡΠΈΠ²Π½ΠΎΠ΅ Π·Π°ΠΏΠΎΠΌΠΈΠ½Π°ΡΡΠ΅Π΅ ΡΡΡΡΠΎΠΉΡΡΠ²ΠΎ, ΡΠ°Π±ΠΎΡΠ°ΡΡΠ΅Π΅ Π² ΡΠΈΠ½Ρ
ΡΠΎΠ½Π½ΠΎΠΌ ΡΠ΅ΠΆΠΈΠΌΠ΅. ΠΠ°Π½Π½ΠΎΠ΅ ΡΡΡΡΠΎΠΉΡΡΠ²ΠΎ Π±ΡΠ΄Π΅Ρ ΡΠ΅Π°Π»ΠΈΠ·ΠΎΠ²Π°Π½ΠΎ Π² Π²ΠΈΠ΄Π΅ ΠΎΡΠ΄Π΅Π»ΡΠ½ΠΎΠ³ΠΎ Π±Π»ΠΎΠΊΠ°, ΡΠΎΠ³Π»Π°ΡΠ½ΠΎ Π΄Π°Π½Π½ΠΎΠΉ ΠΏΠΎ ΡΡΠ»ΠΎΠ²ΠΈΡ Π°ΡΡ
ΠΈΡΠ΅ΠΊΡΡΡΠ΅ ΡΠΈΡΡΠ΅ΠΌΡ. Π Π°ΡΡΠΌΠΎΡΡΠΈΠΌ ΡΠ°Π±ΠΎΡΡ ΠΠΠ£ ΠΈ Π²ΡΠ΅ΠΌΠ΅Π½Π½ΡΠ΅ Π΄ΠΈΠ°Π³ΡΠ°ΠΌΠΌΡ Π΅Π³ΠΎ ΡΠ°Π±ΠΎΡΡ. Π£ΡΠ»ΠΎΠ²Π½ΠΎ-Π³ΡΠ°ΡΠΈΡΠ΅ΡΠΊΠΎΠ΅ ΠΈΠ·ΠΎΠ±ΡΠ°ΠΆΠ΅Π½ΠΈΠ΅ ΠΠΠ£ ΠΏΡΠΈΠ²Π΅Π΄Π΅Π½ΠΎ Π½Π° ΡΠΈΡΡΠ½ΠΊΠ΅ 2.3, Π° Π²ΡΠ΅ΠΌΠ΅Π½Π½Π°Ρ Π΄ΠΈΠ°Π³ΡΠ°ΠΌΠΌΠ° ΡΠ°Π±ΠΎΡΡ — Π½Π° ΡΠΈΡΡΠ½ΠΊΠ΅ 2.4.
Π ΠΈΡΡΠ½ΠΎΠΊ 2.3 — Π£ΡΠ»ΠΎΠ²Π½ΠΎ-Π³ΡΠ°ΡΠΈΡΠ΅ΡΠΊΠΎΠ΅ ΠΈΠ·ΠΎΠ±ΡΠ°ΠΆΠ΅Π½ΠΈΠ΅ ΠΠΠ£.
Π ΠΈΡΡΠ½ΠΎΠΊ 2.4 — ΠΡΠ΅ΠΌΠ΅Π½Π½Π°Ρ Π΄ΠΈΠ°Π³ΡΠ°ΠΌΠΌΠ° ΡΠ°Π±ΠΎΡΡ ΠΠΠ£.
ΠΠ»Ρ ΠΏΡΠΎΠ²Π΅ΡΠΊΠΈ Π±ΡΠ»ΠΈ ΠΏΠΎΠ΄Π°Π½Ρ ΠΈΠ· ΠΏΠΎΡΡΠ° DAT ΠΏΡΠΎΠΈΠ·Π²ΠΎΠ»ΡΠ½ΡΠ΅ Π΄Π°Π½Π½ΡΠ΅ ΠΈ Π·Π°ΠΏΠΈΡΠ°Π½Ρ Π² ΠΠΠ£, Π° ΠΏΠΎΡΠ»Π΅ ΡΡΠΈΡΠ°Π½Ρ.
ΠΠΈΡΡΠΈΠ½Π³ 2.2 ΡΠ΅Π°Π»ΠΈΠ·Π°ΡΠΈΡ VHDL-ΠΊΠΎΠ΄Π° ΠΠΠ£.
USE ieee. std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf. all;
ENTITY lpm_rom0 IS.
PORT.
(.
address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock: IN STD_LOGIC := '1';
q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0).
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS.
SIGNAL sub_wire0: STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram.
GENERIC (.
clock_enable_input_a: STRING;
clock_enable_output_a: STRING;
init_file: STRING;
intended_device_family: STRING;
lpm_hint: STRING;
lpm_type: STRING;
numwords_a: NATURAL;
operation_mode: STRING;
outdata_aclr_a: STRING;
outdata_reg_a: STRING;
widthad_a: NATURAL;
width_a: NATURAL;
width_byteena_a: NATURAL.
);
PORT (.
clock0: IN STD_LOGIC ;
address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
q_a: OUT STD_LOGIC_VECTOR (7 DOWNTO 0).
);
END COMPONENT;
BEGIN.
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component: altsyncram.
GENERIC MAP (.
clock_enable_input_a => «BYPASS» ,.
clock_enable_output_a => «BYPASS» ,.
init_file => «rom. mif» ,.
intended_device_family => «Stratix II» ,.
lpm_hint => «ENABLE_RUNTIME_MOD=NO» ,.
lpm_type => «altsyncram» ,.
numwords_a => 1024,.
operation_mode => «ROM» ,.
outdata_aclr_a => «NONE» ,.
outdata_reg_a => «CLOCK0» ,.
widthad_a => 10,.
width_a => 8,.
width_byteena_a => 1.
).
PORT MAP (.
clock0 => clock,.
address_a => address,.
q_a => sub_wire0.
);
END SYN;